Pulse 280 Specifications download pdf (Page 14)

Operational Description of HRPWM

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Table 4. CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right)

CMPA (count)

(1) (2) (3)

DUTY High CMPA CMPAHR Duty High

% Time (count) (count) (%) Time

(ns) (ns)

28 35.0 280 32 18 40.405 323.24

29 36.3 290 32 19 40.428 323.42

30 37.5 300 32 20 40.450 323.60

31 38.8 310 32 21 40.473 323.78

32 40.0 320 32 22 40.495 323.96

33 41.3 330 32 23 40.518 324.14

34 42.5 340 32 24 40.540 324.32

32 25 40.563 324.50

Required 32 26 40.585 324.68

32.40 40.5 324 32 27 40.608 324.86

(1)

System clock, SYSCLKOUT and TBCLK = 100 MHz, 10 ns

(2)

For a PWM Period register value of 80 counts, PWM Period = 80 x 10 ns = 800 ns, PWM frequency = 1/800 ns = 1.25 MHz

(3)

Assumed MEP step size for the above example = 180 ps

See the device-specific data manual for typical and maximum MEP values.

2.3.2 Scaling Considerations

The mechanics of how to position an edge precisely in time has been demonstrated using the resources

of the standard CMPA and MEP (CMPAHR) registers. In a practical application, however, it is necessary

to seamlessly provide the CPU a mapping function from a per-unit (fractional) duty cycle to a final integer

(non-fractional) representation that is written to the [CMPA:CMPAHR] register combination.

To do this, first examine the scaling or mapping steps involved. It is common in control software to

express duty cycle in a per-unit or percentage basis. This has the advantage of performing all needed

math calculations without concern for the final absolute duty cycle, expressed in clock counts or high time

in ns. Furthermore, it makes the code more transportable across multiple converter types running different

PWM frequencies.

To implement the mapping scheme, a two-step scaling procedure is required.

High-Resolution Pulse Width Modulator (HRPWM) SPRU924F– April 2005– Revised October 2011

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Pulse 280 Specifications Page 14