Pulse 280 Specifications download pdf (Page 27)

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Operational Description of HRPWM

Example 8. PWM DAC Function Initialization Code

void HrPwmDacDrvCnf(void) {

// Config for conventional PWM first

EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // Set Immediate load

EPwm1Regs.TBPRD = 250; // Period set for 400 kHz PWM

hrDAC_period = 250; // Used for Q15 to Q0 scaling

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;

EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master

EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;

EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;

EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

// Note: ChB is initialized here only for comparison purposes, it is not required

EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // optional

EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; // optional

EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;

EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;

EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; // optional

EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // optional

// Now configure the HRPWM resources

EALLOW;

// Note these registers are protected

// and act only on ChA.

EPwm1Regs.HRCNFG.all = 0x0; // Clear all bits first

EPwm1Regs.HRCNFG.bit.EDGMODE = HR_FEP; // Control falling edge position

EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; // CMPAHR controls the MEP.

EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; // Shadow load on CTR=Zero.

EDIS;

MEP_ScaleFactor = 66*256; // Start with typical Scale Factor

// value for 100 MHz.

// Use SFO functions to update

// MEP_ScaleFactor dynamically

}

Example 9 shows an assembly example of run-time code that can execute in a high-speed ISR loop.

SPRU924F– April 2005– Revised October 2011 High-Resolution Pulse Width Modulator (HRPWM)

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Pulse 280 Specifications Page 27